EDA utilizes software tools that may be used in the design and analysis of numerous electronic systems such as printed circuit boards (PCBs) and integrated circuits (ICs). Some EDA tools utilize static timing analysis (STA) as a method to assess the timing of any given digital circuit using software techniques and certain models that provide relevant characteristics of the digital circuit.
Extracted Timing Models (ETMs) are popular hierarchical static timing analysis tools used for hierarchical implementation and signoff. An ETM may refer to an interface timing model of a block, which may be plugged in to a top-level netlist for rapid top-level timing.
Current systems provide the ability to report the timing paths for a given timing arc, which reports the worst timing path used for characterizing an interface arc. If users generally want to look at a specific arc, they need to browse the design and determine the combination of interest which might lead to this arc. This is a cumbersome and counter intuitive way of debugging. More intuitive debugging is based on the arcs, and with arcs specified by user an ETM debugger should be able to get the debug information. Another serious limitation with the current method is that it doesn't explicitly depicts the process of characterization.
Existing systems do not have any arc-based debugging capabilities. With timing model extraction becoming more accurate due to latest technological inclusion, arc based debugging is a necessity. Accordingly, there is a lack of debugging solutions based on arcs in extracted timing models. Existing approaches are merely reporting mechanisms and cannot be used for detailed debugging based on arcs.